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Integrated Circuit Systems, Inc.
ICS1887
FDDI / Fast Ethernet PHYceiverTM
General Description
The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in either FDDI or Fast Ethernet environments. The ICS1887 converts NRZ to/from NRZI data in addition to providing a 5-bit parallel digital data transmit and receive interface. Clock and data recovery is performed on an input serial data stream or the buffered transmit data depending upon the state of the loopback input. A continuous clock source will continue to be present even in the absence of input data. All internal timing is derived from either a low cost crystal, differential or single-ended source. The ICS1887 utilizes advanced CMOS phase-locked loop technology which combines high performance and low power at a greatly reduced cost.
Features
* * * * * * * * * * * * Single IC solution to existing designs requiring multiple devices Data and clock recovery for 125 MBaud FDDI or Fast Ethernet applications Clock multiplication from either a crystal, differential or single-ended timing source Continuous clock in the absence of data No external PLL components Lock/Loss status indicator output Loopback mode for system diagnostics Selectable loop timing mode PECL driver with settable sink current Parallel digital transmit and receive data interface NRZ to/from NRZI data conversion Consult ICS for optional configurations and data rates
Block Diagram
Pin Configuration
28-Pin SOIC
PHYceiver is a trademark of Integrated Circuit Systems, Inc. ICS1887RevF112596
ICS1887
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VSS TXOFF~2 CD~ TX+ TX- VSS IPRG1 RX- RX+ LB~ LOCK RD4 RD3 VSS RD2 RD1 RD0 RCLK VDD REF_IN REF_OUT VDD TCLK TD0 TD1 TD2 TD3 TD4 TYPE TTL-Compatible TTL-Compatible 1 PECL PECL DESCRIPTION Negative Supply Voltage Transmitter Off* Carrier Detect input* Positive Transmit serial data output Negative Transmit serial data output Negative supply voltage PECL Output stage current set (TX) Negative Receive serial data input Positive Receive serial data input Loop Back mode select* Lock detect output Recovered data output 4 Recovered data output 3 Negative supply voltage Recovered data output 2 Recovered data output 1 Recovered data output 0 Recovered Receive clock output Positive supply voltage Positive reference clock/crystal input Negative reference clock/crystal output Positive supply voltage Transmit clock output Transmit data input 0 Transmit data input 1 Transmit data input 2 Transmit data input 3 Transmit data input 4
PECL PECL TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible
TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible TTL-Compatible
* Active Low Input.
Note:
1. A running production change will be made to this input in the June 1996 time frame to convert this input from the TTL-compatible to PECL to more closely match applications requirements. See Substituting the ICS1887 for the AMD PDR & PDT applications note for more information. 2. This pin was formerly used for Loop-Timed operation. If your design did not use loop timing, this change does not affect you. If your application requires loop timing, please contact ICS.
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ICS1887
Input Pin Descriptions
Parallel Transmit Data (TD0 .. TD4)
Five bit TTL compatible digital input, which is received by the ICS1887 on the positive edge of TCLK. High impedance input drivers routed to the serial NRZ to NRZI converter. In loopback testing mode, this NRZI data is multiplexed to the input of the device clock recovery section.
Receive Clock (RCLK)
A 25 MHz digital clock recovered with the internal clock recovery PLL. In loopback mode this clock is recovered from the transmit data.
Lock/Loss Detect (LOCK)
Set high when the clock recovery PLL has locked onto the incoming data. Set low when there is no incoming data, which in turn causes the PLL to free-run. This signal can be used to indicate or `alarm' the next receive stage that the incoming serial data has stopped.
Differential ECL Receive Data Input (RX+ & RX-)
The clock recovery and data regenerator from the receive buffer are driven from this PECL input. During loopback testing mode this input is ignored.
Output Description
The differential driver for the TX is current mode and is designed to drive resistive terminations in a complementary fashion. The output is current-sinking only, with the amount of sink current programmable via the IPRG1 pin. The sink current is equal to four times the IPRG1 current. For most applications, an 910 resistor from VDD to IPRG1 will set the current to the necessary precision. The TX pins are incapable of sourcing current, so VOH must be set by the ratios of the Thevenin termination resistors for each of these lines. R1 is a pull-up resistor connected from the PECL output to VDD. R2 is a pull-down resistor connected from the PECL output to VSS. R1 and R2 are electrically in parallel from an AC standpoint. If we pick a target impedance of 50 for our transmission line impedance, a value of 62 for R1 and a value of 300 for R2 would yield a Thevinin equivalent characteristic impedance of 50 and a VOH value of VDD -.88 volts, compatible with PECL circuits. To set a value for VOL, we must determine a value for Iprg that will cause the output FET's to sink an appropriate current. We desire VOL to be VDD -1.81 or greater. Setting up a sink current of 19 milliamperes would guarantee this through our output terminating resistors. As this is controlled by a 4/1 current mirror, 4.75 mA into Iprg should set this current properly. An 910 resistor from VDD to Iprg should work fine.
Carrier Detect (CD~)
Active low input which forces the VCO to free run. Upon receipt of a loss of input signal (such as from an optical-toelectrical transducer), the internal phase-lock loop will free-run at the selected operating frequency. Also, when asserted, CD will set the lock output low.
Transmitter Off (TXOFF~)
Active low input which, when low, forces TX+ low and TX-high. When high, data passes through TX+ and TXunaffected. This input has an internal pull-up resistor.
Loopback Mode (LB~)
Active low input which causes the clock recovery PLL to operate using the transmit input data reference and ignore the receive RX data. Utilized for system loopback testing.
External Crystal or Reference Clock (REF_IN and REF_OUT)
This oscillator input can be driven from either a fundamental mode crystal or a stable reference. For either method, the reference frequency is 25.00 MHz.
Output Pin Descriptions
Differential ECL Transmit Data (TX+ and TX-)
This differential output is converted TD[0..4] serial data. This output remains active during loopback mode.
Transmit Clock (TCLK)
TTL compatible 25 MHz clock used by the parallel processor transmitter for clocking out transmit data. This clock can be derived from either an independent clock source or from the recovered data clock (system loop time mode).
Parallel Receive Data (RD0 .. RD4)
The regenerated five bit parallel data derived from the serial data input. In loopback mode this data is regenerated from the transmit data. This data is phase-aligned with the negative edge of RCLK clock output.
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ICS1887
ICS1887 System Diagram
(PECL Termination for 50 Transmission Lines)
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ICS1887
Substituting the ICS1887 for the AMD PDR & PDT CD PECL Input: Board Layout Options
This note describes the issues involved in replacing the AMD PDR & PDT with the ICS1887. There are a number of implementation differences between AMD's PDR & PDT and the ICS1887. This note describes the differences and how they affect an application.
Option 1
Differential PECL to CMOS Conversion Circuit
Signal Detect
Many twisted pair and fiber optic transceivers provide a signal detect indication that becomes active when the amount of energy being received reaches a threshold that makes it appear to be data and not ambient noise. The AMD PDR device has a single ended PECL input (SDI) and provides a TTL level output (SDO) that tracks the input. The input controls the source that the PLL locks to. When signal detect is asserted, the PLL locks to the incoming receive data. When signal detect is deasserted, the PLL locks to the LSCLK input to prevent locking to an off center frequency. The current ICS1887 device provides a single TTL-compatible input, carrier detect (CD~). When carrier detect is asserted, the ICS1887 locks to the incoming receive data. When carrier detect is deasserted, or if carrier detect is asserted and no data is present on the receive inputs, the PLL will free run and continue to provide RXCLK at the nominal 25 MHz frequency. This allows the carrier detect input to always be tied to an asserted level (ground). If a true signal detect is required by a chip that connects to the ICS1887, a simple, low cost PECL to CMOS converter can be used. The following circuit implements this function:
Option 2
Single-Ended PECL to CMOS Conversion Circuit
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ICS1887
This circuit provides the PECL to CMOS conversion for less than $0.80 in single unit quantities. Note that the LM393 has two amplifiers, so the unused one is tied inactive. A running production change will be made to the ICS1887 to change the CD input to PECL. Therefore, boards should be laid out with a direct normal PECL termination connection stuffing option. This allows either version of the part to be used by stuffing one of two sets of external components. A version of this circuit is shown in the diagram on the previous page. With ICS1887 devices that have a TTL-compatible CD input, the "Differential PECL to CMOS Conversion Circuit" components need to be placed on the PCB and the "Normal PECL Transceiver Termination" resistors (82 and 130) as well as the option select jumper should NOT be placed. When the final ICS1887 device with the PECL CD input is used, none of the components in the "Differential PECL to CMOS Conversion Circuit" or the "Unused amp connection" circuits should be used. Only the four termination resistors (87 and 130) and the option select jumper are needed. Note that these resistors should be located near the ends of the transmission lines.
Loopback
The AMD PDR & PDT chips have an external loopback connection between the two chips. The ICS1887 also has a loopback function, but it is totally internal to the device.
Optical Transmitter Off Control
The PDT chip has an input (FOTOFF) which can force an optical transceiver to be off. The ICS1887 performs the same behavior with the TXOFF~ pin.
Test Mode
Both the AMD PDR & PDT have a test mode that allows automated testers to test internal logic without the PLL clock multiplier. The ICS1887 does not have a similar test mode.
Transmit Current Selection
The ICS1887 allows the PECL transmit current level to be set externally. An 887 resistor to the VDD supply is recommended.
Clocking
Parallel data that is to be serialized for transmission must be presented to the data transmitter device with a certain amount of setup and hold time to a given clock. The PDT chip expects data to setup relative to the 25 MHz Local Symbol Clock (LSCLK). This clock is an input to the device. The ICS1887 expects data to be setup relative to the 25 MHz Reference In Clock (REF_IN). This clock is an input to the ICS1887 device. Note that the REF_IN pin of the ICS1887 is a CMOS input with a switching point of 50% of VDD. If this pin is driven by a TTL output, a pull-up resistor to VDD must be used. The ICS1887 device also provides a Transmit Clock (TXC) output, which is a 50% duty cycle (nominal) copy of the REF_IN input. The ICS1887 is designed to provide a very low skew between the REF_IN and the TCLK.
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ICS1887
Absolute Maximum Ratings
VDD (measured to VSS) . . . . . . . . . . . . . . . . . . 7.0 V Digital Inputs/Outputs . . . . . . . . . . . . . . . . . . VSS - 0.5 V to VDD + 0.5 V Ambient Operating Temperature . . . . . . . . . . - 55 C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . - 65 C to +150 C Junction Temperature . . . . . . . . . . . . . . . . . . . 175C Soldering Temperature . . . . . . . . . . . . . . . . . . 260 C
Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER Ambient Operating Temp. Using a Positive Supply SYMBOL TEST CONDITIONS TA VSS VDD MIN 0 0.0 +4.50 MAX +70 0.0 +5.50 UNITS C V V
ICS1887 FDDI / Fast Ethernet Application
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ICS1887
DC Characteristics
VDD = VMIN to VMAX , VSS = 0V, TA = TMI N to TMAX PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = +5.0V, VSS = 0.0V MIN -- MAX 80 UNITS mA
ECL Input / Output
PARAMETER ECL Input High Voltage ECL Input Low Voltage ECL Differential Threshold Voltage Range ECL Input Common Mode Voltage ECL Output High Voltage ECL Output Low Voltage SYMBOL VIH VIL VT H VC M VOH VOL CONDITIONS MIN VDD -1.16 VDD -1.81 -- 1.3 VDD -1.02 -- MAX VDD -0.88 VDD -1.47 150 VDD - .4 -- VDD -1.62 UNITS V V mV V V V
TTL Input / Output
PARAMETER TTL Input High Voltage TTL Input Low Voltage TTL Output High Voltage TTL Output Low Voltage TTL Driving CMOS Output High Voltage TTL Driving CMOS Output Low Voltage TTL / CMOS Output Sink Current TTL / CMOS Output Source Current SYMBOL VIH VIL VOH VOL VOH VOL IOL IOH CONDITIONS VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V MIN 2.0 -- 2.4 -- 3.68 -- 8 -- MAX -- 0.8 -- 0.4 -- 0.4 -- -0.4 UNITS V V V V V V mA mA
REF_IN Input
PARAMETER Input High Voltage Input Low Voltage SYMBOL VIH VIL CONDITIONS VDD = 5.0V, VSS = 0.0V VDD = 5.0V, VSS = 0.0V MIN 3.5 -- MAX -- 1.5 UNITS V V
Note: REF_IN Input switch point is 50% of VDD.
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ICS1887
AC Characteristics Clocks - Reference In (REF_IN) to Transmit Clock (TCLK)
T# t1 t2 t3
PARAMETER (conditions) REF_IN Duty Cycle REF_IN Period REF_IN rise to TCLK rise
MIN 45 -- 0
TYP 50 40 1.5
MAX 55 -- 3.0
UNITS % ns ns
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ICS1887
Clocks -- Transmit Clock Tolerance
T# t1 t2
PARAMETER (conditions) TCLK Duty Cycle TCLK Period
MIN 40 --
TYP 50 40
MAX 60 --
UNITS % ns
Note: TCLK Duty cycle = REF_IN Duty cycle 5%.
Clocks -- Receive Clock Tolerance
T# t1 t2
PARAMETER (conditions) RCLK Duty Cycle RCLK Period
MIN 45 --
TYP 50 40
MAX 55 --
UNITS % ns
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ICS1887
5-Bit Interface - Synchronous Transmit Timing
T# t1 t2
PARAMETER (conditions) TD[4:0] Setup to TCLK rise TD[4:0] Hold after TCLK rise
MIN 10 0
TYP -- --
MAX -- --
UNITS ns ns
5-Bit Interface - Synchronous Receive Timing
T# t1 t2
PARAMETER (conditions) RD[4:0] Setup to RCLK rise RD[4:0] Hold after RCLK rise
MIN 13.0 12.5
TYP -- --
MAX -- --
UNITS ns ns
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ICS1887
Transmit Latency
T# t1
PARAMETER (conditions) TD[4:0] sampled to TX+ Output of 1st bit
MIN --
TYP --
MAX 5
UNITS bits
Receive Latency
T# t1
PARAMETER (conditions) MSbit into RX+ to MSb on RD[4:0]
MIN --
TYP --
MAX 8
UNITS bits
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ICS1887
Clock Recovery
T# t1 t2 t3 t4
PARAMETER (conditions) Ideal data recovery window Actual data recovery window Data recovery window truncation CD assert to data acquired
MIN -- 6 0 --
TYP -- -- -- --
MAX 8 8 1 5
UNITS ns ns ns s
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ICS1887
SOIC PACKAGE
LEAD COUNT DIMENSION L 28L 0.704
Ordering Information ICS1887M
Example:
ICS XXXX M
Package Type M = SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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